1. Field of the Invention
The method and apparatus of the present invention is directed to a co-processor de-coupling bus for communications between processors.
2. Art Background
To increase the efficiency of a system, it is quite common to provide multiple or co-processors in addition to a main processor and off-load predetermined functions or computations to the co-processors in order to decrease the processing overhead of the main processor. These co-processors are often specialized for a particular task or type of task. For example, math co-processors and graphics co-processors are widely used. The co-processor typically functions as a slave to the master or main CPU. Communications between the co-processors are achieved through a bus, shared memory or a combination of the two.
Typically, a separate shared memory is provided for communication of data and instructions between processors. A polling and/or interrupt mechanism is provided in each processor such that each processor knows when instructions and/or data is placed in the shared memory to be accessed by the processor. To save on space and achieve the greatest memory utilization, a single memory such as a dynamic random access memory (DRAM) is used to provide memory for storage of code and data utilized by the co-processor to perform its tasks. The memory functions as the shared memory utilized for communications between the host processor and co-processor. For example, as shown in FIG. 1, DRAM 10 is used for storing data communicated between the main processor 20 and co-processor 30 via a shared memory 40 as well as for storing the code and data utilized by co-processor 30.
As the co-processor 30 is using the memory for storage of code to be executed by the co-processor as well as storage of data to perform the functions, the co-processor will be accessing the memory quite frequently. However, while the co-processor 30 is accessing the DRAM 10 to retrieve code or data 50, the main processor 20 is attempting to also access the DRAM 10 in order to communicate information to the co-processor 30 or retrieve information from the co-processor 30 through the shared memory 40. Thus, an arbitration mechanism 60 is required to determine which access will be permitted as only one access to the physical DRAM chip may be performed at any time.
However, both processors are slowed down measurably due to the inefficient utilization of the DRAM subsystem. For example, it is likely that the physical locations of memory accessed by the main processor and co-processor are far apart in the address space of the memory. The accesses by the main processor and co-processor are therefore likely to result in a large number of "far" cycles. A far cycle occurs when the page mode of the memory subsystem cannot be used. Thus, the number of far accesses to the memory array by both processors is increased.
In order to gain the system performance benefit from the use of a co-processor, the time required for communicating instructions and data from the main processor 20 to the co-processor 30, executing the instruction by the co-processor 30 and communicating the results of the execution to the main processor 20 must be less than the time required for the main processor itself to execute the instructions. Therefore it is quite important that the communications are performed as efficiently as possible with minimal effect on the performance of the co-processor 30.